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mos integrated circuit m m m m pd16432b 1998 ? document no. s11092ej5v0ds00 (5th edition) date published april 1998 n cp(k) printed in japan data sheet 1/8, 1/15 duty lcd controller/driver description the m pd16432b is a controller/driver with 1/8 and 1/15 duty dot matrix lcd display capability. it has 60 segment outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12 columns 2 lines (at 1/15 duty). led drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use in a car stereo front panel, etc. features ? dot matrix lcd controller/driver ? pictograph display segment drive capability (max. 64) ? lcd driver unit power supply v lcd independently settable (max. 10 v) ? on-chip key scan circuit (8 4 matrix) ? alphanumeric character and symbol display capability provided by on-chip rom (5 7 dots) 240 characters + 16 user-defined characters ? display contents 1/8 duty: 13 columns 1 line, 64 pictograph displays, 4 leds 1/15 duty: 12 columns 2 lines, 60 pictograph displays, 4 leds ? serial data input/output (sck, stb, data) ? on-chip oscillator ? reduced power consumption possible using standby mode ordering information part number package m pd16432bgc-001-9eu 100-pin plastic qfp (0.5 pitch, 14 14), standard rom code
2 m m m m pd16432b block diagram led driver led 1 led 4 4 4-bit led output latch 4 4 stb sck data serial i/f reset lcd off sync segment driver 65-bit output latch 65 65 seg 1 /ks 1 seg 8 /ks 8 seg 9 seg 60 seg 61 /com 14 seg 65 /com 10 5 65-bit shift register parallel/serial conversion cg ram 5 7 16 5 cg rom 5 7 240 5 8 display data ram 8 25 8 5 character display ram 64 bits 8 common driver 15-bit shift register 15 com 9 com 0 5 5 timing generator 2 osc in osc osc out key data ram 4 8 key 1 key 4 command decoder key req v dd v ss v lcd v lc1 v lc2 v lc3 v lc4 v lc5
3 m m m m pd16432b pin configuration seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 seg 43 seg 42 seg 41 seg 40 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 led 1 led 2 led 3 led 4 v ss v lc5 v lc4 v lc3 v lc2 v lc1 v lcd v dd sync lcd off reset key req sck data stb osc in osc out key 1 key 2 key 3 key 4 seg 25 seg 24 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 /ks 8 seg 7 /ks 7 seg 6 /ks 6 seg 5 /ks 5 seg 4 /ks 4 seg 3 /ks 3 seg 2 /ks 2 seg 1 /ks 1 seg 51 seg 52 seg 53 seg 54 seg 55 seg 56 seg 57 seg 58 seg 59 seg 60 seg 61 /com 14 seg 62 /com 13 seg 63 /com 12 seg 64 /com 11 seg 65 /com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com 1 com 0 75 51 125 26 50 100 76
4 m m m m pd16432b pin descriptions pin symbol pin name pin no. function seg 1 /ks 1 to seg 8 /ks 8 segment output/key source output dual-function pins 26 to 33 pins with dual function as dot matrix lcd segment outputs and key scanning key source outputs seg 9 to seg 60 segment outputs 34 to 85 dot matrix lcd segment outputs seg 61 /com 14 to seg 85 /com 10 segment output/common output dual-function pins 86 to 90 switchable to either dot matrix lcd segment outputs or com- mon outputs com 0 to com 9 common outputs 91 to 100 dot matrix lcd common outputs led 1 to led 4 led output pins 1 to 4 led outputs are nch open-drain. sck shift clock input 17 data shift clock data is read on rising edge, and output on falling edge. data data input/output 18 performs input of commands, key data, etc., and key data output. input is performed from the msb on the rise of the shift clock, and the first 8 bits are recognized as a command. output is performed from the msb on the fall of the shift clock. output is nch open-drain. stb strobe input 19 data input is enabled when h. command processing is performed on a fall. key req key request output 16 h if there is key data, l if there is none. key data can be read irrespective of the state of this pin. output is cmos output. reset reset input 15 initial state is set when l. lcd off lcd off input 14 when l, a forced lcd off operation is performed, and seg n & com n output the unselected waveform. sync synchro 13 synchronization signal input/output pin. when 2 or more chips are used, wired-or connection is made to each chip. a pull-up resistor is also required when one chip is used. osc in 20 osc out oscillation pins 21 connect oscillator resistor. key 1 to key 4 key data inputs 22 to 25 key scanning key data inputs. v dd logic power supply pin 12 internal logic power supply pin v ss gnd pin 5 gnd pin v lcd lcd drive voltage pin 11 lcd drive power supply pin v lc1 to v lc5 lcd drive power supply 10 to 6 dot matrix lcd drive power supply
5 m m m m pd16432b lcd display in the m pd16432b lcd display, a 5 7-segment display and pictograph display segments can be driven. the pictograph display segment common output is allocated to com 0 , and up to 64 can be driven. (1) example of 1/8 duty connections 1 64 pictograph segments seg com1 com2 com3 com4 com5 com6 com7 com0 2345 61 62 63 64 65 678910 (2) example of 1/15 duty connections 1 seg com1 com2 com3 com4 com5 com6 com7 2345 56 57 58 59 60 678910 60 pictograph segments com8 com9 com10 com11 com12 com13 com14 com0
6 m m m m pd16432b character codes and character patterns the relation between character codes and character patterns is shown below. character codes 00h to 0fh are allocated to cgram. character codes 10h to 1fh and e0h to ffh are undefined. x0hram higher bits 0xh cg (1) 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh axh bxh cxh dxh exh fxh lower bits x1hram cg (2) x2hram cg (3) x3hram cg (4) x4hram cg (5) x5hram cg (6) x6hram cg (7) x7hram cg (8) x8hram cg (9) x9hram cg (10) xahram cg (11) xbhram cg (12) xchram cg (13) xdhram cg (14) xehram cg (15) xfhram cg (16)
7 m m m m pd16432b display ram addresses display ram addresses are allocated as shown below irrespective of the display mode. column no.12345678910111213 line 1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch line 2 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h pictograph display ram addresses pictograph display ram addresses are allocated as shown below. segment output no. address b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 note when 1/15 duty is used (12 columns 2 lines), 61 to 64 are disabled.
8 m m m m pd16432b cgram column addresses a maximum of any sixteen 5 7-dot characters can be written in cgram. the row address within one character is allocated as shown below, and is specified by bits b7 to b5. the character code for which a write is to be performed must be specified beforehand with an address setting command. dot data row address b7 b6 b5 b4 b3 b2 b1 b0 00h 0 0 0 ***** 01h 0 0 1 ***** 02h 0 1 0 ***** 03h 0 1 1 ***** 04h 1 0 0 ***** 05h 1 0 1 ***** 06h 1 1 0 ***** row address font data (5 7 dots) * font data (1: on, 0: off)
9 m m m m pd16432b key matrix and key data ram configuration the key matrix has an 8 4 configuration, as shown below. key 1 key 2 key 3 key 4 ks 1 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 = key data is stored as shown below, and is read in msb-first order by a read command. b7 b4 b3 ks 7 read order ks 5 key 1 key 2 key 3 key 4 ks 3 ks 1 b0 ks 8 ks 6 ks 4 ks 2 key data is as follows: 1: on 0: off ? key input equivalent circuit key n v dd r pull-up control signal to key data ram in the event of key source output, the pull-up control signal becomes ?? and the pull-up transistor is turned on.
10 m m m m pd16432b key request (key req) a key request is output as shown below according to the state. state key req note key scan internal pull-up resistor in key scan operation high level is output while any key data is 1. note during key scan : on during display : off in standby mode or when seg n & com n are fixed at v lc5 high level is output in case of key input only. always on when key scanning is stopped fixed at low level always off note key req does not become low until the key data is all 0. (it is not synchronized with the key data reads.) led output latch configuration the low-order 4 bits of the led output latch are enabled, and the high-order 4 bits disabled, as shown below. b3 b2 b1 b0 lsb msb : don? care led 1 led 2 led 3 led 4 latch data is as follows: 1: on 0: off ?
11 m m m m pd16432b commands commands set the display mode and status. the first byte after a rise edge on the stb pin is regarded as a command. if stb is driven low during command/data transfer, serial communication is initialized and the command/data being transferred is invalidated. (however, a command or data that has already been transferred is valid.) (1) display setting command this command initializes the m pd16432b note , and sets the duty, number of segments, number of commons, master/ slave operation, and the drive voltage supply method. the state set when this command is executed is: lcd off, led on, key scanning stopped. to restart the display, it is necessary to execute status command normal operation. however, nothing is done if the same mode is selected. b2 b1 b0 0 0 lsb msb : don? care duty setting 0: 1/8 duty (seg61/com14 to seg65/com10 ? segment outputs) 1: 1/15 duty (seg61/com14 to seg65/com10 ? common outputs) master/slave setting 0: master 1: slave drive voltage supply method selection 0: external 1: internal 000 after powering on note when multiple chips are used, only the chip that sent the command is enabled. if initialization is performed during display, the display may be affected (especially when multiple chips are used).
12 m m m m pd16432b (2) data setting command sets the data write mode, read mode, and address increment mode. b3 b2 b1 b0 1 0 lsb msb : don? care data write mode/read mode setting 000: write to display data ram 001: write to character display ram 010: write to cgram 011: write to led output latch 100: read key data address increment mode setting (display data ram, character display ram) 0: increment after data write 1: address fixed 0000 after powering on (3) address setting command sets the display data ram or character display ram address. b3 b2 b1 b0 b4 0 1 lsb msb : don? care address display data ram character display ram cgram 0000 0 after powering on : 00h to 18h : 00h to 07h : 00h to 0fh note if an unspecified address is set, data cannot be written until a correct address is next set. the address is not incremented even in increment mode.
13 m m m m pd16432b (4) status command controls the status of the m pd16432. b3 b2 b1 b0 b4 b5 1 1 lsb msb lcd cotrol 00: lcd forced off (segn, comn = v lc5 ) 01: lcd forced off (segn, comn = unselected waveform) 10: normal operation 11: normal operation led control 0: led forced off 1: normal operation key scan control 0: key scanning stopped 1: key scan operation test mode setting 0: normal operation 1: test mode standby mode setting 0: normal operation 1: standby mode ? ? ? ? ? ? ? y ? ? ? ? ? ? ? t note 0000 0 0 after powering on note the following states are use prohibited modes, and key scanning does not operate if these states are set. 1000 0 0 1100 0 0
14 m m m m pd16432b standby mode if standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0 of the status command. (1) lcd forced off (seg n , com n = v lc5 ) (2) led forced off (3) key scanning stopped (but key n = key input wait) (4) osc stopped there are two ways of releasing standby mode, as follows: (1) using status command select normal operation with bit b4 of the status command. example of use of status command command/data item stb b7 b6 b5 b4 b3 b2 b1 b0 description standby mode l status command h 1 1 0 0 0 0 0 0 standby release (osc oscillation start), lcd control off (seg n , com n = v lc5 ), led forced off, key scanning stopped standby transition time l 10 m s note status command h 1 1 0 0 1 1 1 0 normal operation end l note if lcd normal operation or key scan operation is initiated within the standby transition time, the lcd may flicker.
15 m m m m pd16432b (2) using key n if any key is set to the on state, the standby mode is released and osc oscillation starts. also, key req is set to h, informing the microcomputer that a key has been pressed and standby mode has been released. in this state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after the standby transition time, and fetch the key data. example of use of key n command/data item stb b7 b6 b5 b4 b3 b2 b1 b0 description standby mode l key data present l standby release (key req = h, osc oscillation start) standby transition time l 10 m s note status command h 1 1 0 0 1 0 0 1 lcd forced off (unselected waveform), led forced off, key scan operation key scan l 1 frame or more data setting command h 0 1 0 0 0 1 0 0 key data read, address increment key data h ******** for ks 8 , ks 7 key data h ******** for ks 6 , ks 5 key data h ******** for ks 4 , ks 3 key data h ******** for ks 2 , ks 1 end l key distinction note if lcd normal operation or key scan operation is initiated within the standby transition time, the lcd may flicker.
16 m m m m pd16432b serial communication formats (1) reception (command/data write) sck 123 678 data b7 stb b6 b5 b1 b0 b2 if data continues (2) transmission (command/data read) sck data stb 1 2 3 6 7 8 1 2 3 4 5 6 b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 1 s m wait time t wait data read data read command setting caution as the data pin is an nch open-drain output, a pull-up resistor must be connected externally. (1 k w w w w to 10 k w w w w )
17 m m m m pd16432b absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol rating unit logic supply voltage v dd C0.3 to +7.0 v logic input voltage v in C0.3 to +v dd + 0.3 v logic output voltage (dout, led) v out C0.3 to +7.0 v lcd drive supply voltage v lcd C0.3 to +12.0 v lcd drive power supply input voltage v lc1 to v lc5 C0.3 to +v lcd + 0.3 v driver output voltage (segment, common) v out2 C0.3 to +v lcd + 0.3 v led drive current i ol1 20 ma package allowable dissipation p t 1000 mw operating ambient temperature t a C40 to +85 c storage temperature range t stg C55 to +150 c recommended operating ranges parameter symbol min. typ. max. unit logic supply voltage v dd 2.7 5.0 5.5 v lcd drive supply voltage v lcd v dd 8.0 10.0 v logic input voltage v in 0v dd v driver input voltage v lcd1 to v lcd5 0v lcd v led drive current i ol1 15 ma
18 m m m m pd16432b electrical specifications (unless specified otherwise, t a = C40 to +85c, v dd = 5 v 10%, v lcd = 8 v 10%) parameter symbol test conditions min. typ. max. unit high-level input voltage v ih 0.7 v dd v dd v low-level input voltage v il 0 0.3 v dd v high-level input current i ih sck, stb, lcdoff, reset, key 1 to key 4 1 m a low-level input current i il sck, stb, lcdoff, reset, key 1 to key 4 C1 m a low-level output voltage v ol1 led 1 to led 4 , i ol1 = 15 ma 1.0 v high-level output voltage v oh2 osc out , key req, i oh2 = C1 ma 0.9 v dd v low-level output voltage v ol2 data, osc out , sync, i ol2 = 4 ma 0.1 v dd v high-level leak current i loh2 data, sync, v in/out = v dd 1 m a low-level leak current i lol2 data, sync, v in/out = v ss C1 m a common output on- resistance r com v lcd to v lc5 ? com 0 to com 14 , | i o | = 100 m a2.4k w segment output on- resistance r seg v lcd to v lc5 ? seg 1 to seg 60 , | i o | = 100 m a4.0k w i dd1 normal operation note , v i = v dd or v ss , f osc = 250 khz 500 m a current consumption (logic) i dd2 standby mode, v i = v dd or v ss , f osc stopped 5 m a i lcd1 normal operation, internal bias selected, no load 1 000 m a current consumption (driver) i lcd2 standby mode, internal bias used, no load 5 m a note normal operation: v dd = 5 v, v lcd = 8 v remarks typ. values are reference values for t a = 25c.
19 m m m m pd16432b switching specifications (unless specified otherwise, t a = C40 to +85c, v dd = v lcd = 5 v 10%, r l = 5 k w w w w , c l = 150 pf) parameter symbol test conditions min. typ. max. unit oscillator frequency f osc r = 100 k w 175 250 325 khz output data delay time t pzl sck ? data 100 ns output data delay time t plz sck ? data - 300 ns sync delay time t dsync 1.5 m s note the time for one frame is found as follows. 1 frame = 1/f osc 128 clocks duty number + 1/f osc 64 clocks if f osc = 250 khz and duty = 1/15, 1 frame = 4 m s 128 15 + 4 m s 64 = 7.94 ms required timing conditions (unless specified otherwise, t a = C40 to +85c, v dd = 5 v 10%, v lcd = 8 v 10%, r l = 5 k w w w w , c l = 150 pf) parameter symbol test conditions min. typ. max. unit clock frequency f osc osc in external clock 100 500 khz high-level clock pulse width t whc osc in external clock 1 5 m s low-level clock pulse width t wlc osc in external clock 1 5 m s shift-clock cycle t cyk sck 900 ns high-level shift clock pulse width t whk sck 400 ns low-level shift clock pulse width t wlk sck 400 ns shift clock hold time t hstbk stb - ? sck 1.5 m s data setup time t ds data ? sck - 100 ns data hold time t dh sck - ? data 200 ns stb hold time t hkstb sck - ? stb 1 m s stb hold time t wstb 1 m s wait time t wait 8th sck - ? 9th sck , in data read 1 m s sync removal time t srem 250 ns standby transition time t pstb 10 m s reset pulse width t wrs reset 0.1 m s power-on reset time t pon from power-on 4 clk
20 m m m m pd16432b output load circuit v dd 5 k w 150 pf data switching specification waveform diagrams osc in v il v ih 1/f c t whc t wlc v ih v ih v il t hstbk t wstb t cyk t wlk t wlk v il v ih v il v ih t ds t dh t hkstb stb sck data
21 m m m m pd16432b switching specification waveform diagrams f osc sync internal reset one frame one frame sync timing (master) t dsync one frame one frame sync timing (slave) t srem t pzl v il v ol2 t plz sck data reset reset t wre
22 m m m m pd16432b output waveforms (1) 1/8 duty (1/4 bias: vlc2: vlc3) v lcd v lc1 v lc2 v lc4 v lc5 com 0 0 1 2 3 4 5 6 7 k 0 1 * v lcd v lc1 v lc2 v lc4 v lc5 com 1 v lcd v lc1 v lc2 v lc4 v lc5 com 7 v lcd v lc1 v lc2 v lc4 v lc5 seg 2 v lcd v lc1 v lc2 v lc4 v lc5 seg 1 v lcd 3/4v lcd 2/4v lcd ?/4v lcd ?/4v lcd seg 1 -com 1 ?/4v lcd 1/4v lcd 0 ? lcd v lcd 3/4v lcd 2/4v lcd ?/4v lcd ?/4v lcd seg 1 -com 0 ?/4v lcd 1/4v lcd 0 ? lcd 256 s 512 s m m 4.4 ms * key scan period
23 m m m m pd16432b enlargement of key scan period 7 1 2 3 4 5 6 7 8 0 v lcd v lc1 v lc2 v lc4 v lc5 seg 1 k seg 1 v lcd v lc1 v lc2 v lc4 v lc5 com 0 v lcd v lc1 v lc2 v lc4 v lc5 seg 2 v lcd v lc1 v lc2 v lc4 v lc5 seg 8 v lcd v lc1 v lc2 v lc4 v lc5 seg 9 to seg 65 = key source output
24 m m m m pd16432b (2) 1/15 duty (1/5 bias) 256 s v lcd v lc1 v lc2 v lc3 v lc4 com 0 1/2v lcd v lc5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 k 1 2 * * key scan period v lcd v lc1 v lc2 v lc3 v lc4 com 1 1/2v lcd v lc5 v lcd v lc1 v lc2 v lc3 v lc4 com 14 1/2v lcd v lc5 v lcd v lc1 v lc2 v lc3 v lc4 seg 1 v lc5 v lcd 3/5v lcd 1/2v lcd ?/5v lcd ?/2v lcd seg 1 -com 0 ?/5v lcd 1/5v lcd 0 ? lcd 512 s m m 7.9 ms
25 m m m m pd16432b enlargement of key scan period seg 9 to seg 65 seg 8 seg 2 14 1 2 3 4 5 6 7 8 0 v lc5 v lc1 v lc2 v lc3 v lc4 seg 1 k v lcd v lc1 v lc2 v lc3 v lc4 com 0 v lc5 v lc1 v lc2 v lc3 v lc4 v lcd v lc1 v lc2 v lc4 v lc5 v lc1 v lc2 v lc3 v lc4 v lc5 = key source output v lcd v lc5 v lcd 1/2v lcd v lcd v lc3
26 m m m m pd16432b access procedures access procedures are illustrated below by means of flowcharts and timing charts. 1. initialization (1) flowchart 0101 0 0 0 0 lsb msb display setting command (command 1) (1/15 duty, master, internal drive) initial state initialization 1001 0 0 1 1 lsb msb status command (command 2) (lcd off, led off, key scan operation) key scan start 0000 0 0 1 0 lsb msb data setting command (command 3) (display data ram, increment) display data ram write 0000 0 0 0 1 lsb msb address setting command (command 4) (display data ram: 0h) address setting start display data 0001 0 0 1 0 lsb msb data setting command (command 5) (character display ram, increment) character display ram write character data all data written? all data written? no no yes yes
27 m m m m pd16432b 0011 0 0 1 0 lsb msb data setting command (command 6) (led latch, increment) led output latch write led data 1110 0 0 1 1 lsb msb status command (command 7) (lcd on, led on, key scan operation) to next processing lcd, led on (2) timing chart data sck stb command 1 command 2 command 3 command 4 data 1 data sck stb data n-1 data n command 5 data 1 data sck stb data n command 6 data command 7
28 m m m m pd16432b 2. display data rewrite (address setting) (1) flowchart 1000 0 0 1 0 lsb msb data setting command (command 1) (display data ram, address fixed) display data ram write 0101 0 0 0 1 lsb msb address setting command (command 2) (display data ram: 5h) address setting to next processing display data start (2) timing chart data sck command 1 command 2 data stb
29 m m m m pd16432b 3. key data read (1) flowchart key req recognition start 0100 0 0 1 0 lsb msb data setting command (command 1) (key data) key req = h? no yes key data read wait ok? no yes all data read? no yes to next processing key data wait time: 1 s m (2) timing chart data sck stb command 1 data 1 data 2 data 3 key req data sck stb data 4 key req t wait cautions 1. wait time t wait (1 m m m m s) is necessary from the rise of the 8th shift clock of command 1 until the fall of the 1st shift clock of data 1. 2. key req does not become low until the key data is all 0. (it is not synchronized with the key data reads.)
30 m m m m pd16432b 4. cgram write (1) flowchart 0010 0 0 1 0 lsb msb data setting command (command 1) (cgram, increment) 0000 0 0 0 1 lsb msb address setting command (command 2) (cgram character code: 0h) address setting cgram data start to next processing all data written? no yes cgram write (2) timing chart data sck stb command 1 command 2 data 1 data 2 data sck stb data 6 data 7
31 m m m m pd16432b 5. standby (released by status command) (1) flowchart 0000 1 0 1 1 lsb msb status command (command 1) (standby) 0000 0 0 1 1 lsb msb status command (command 2) (standby release) standby release to next processing normal operation start 1110 0 0 1 1 lsb msb status command (command 3) (lcd on, led on, key scan operation) transition time ok? no standby transition time: 10 s standby m yes (2) timing chart data sck stb command 1 command 2 command 3 t stby
32 m m m m pd16432b 6. standby (released by key n ) (1) flowchart key (key n ) input ? key req = h, osc oscillation start 0000 1 0 1 1 lsb msb status command (command 1) (standby) key request to next processing normal operation start 1110 0 0 1 1 lsb msb status command (command 2) (lcd on, led on, key scan operation) transition time ok? no standby transition time: 10 s standby m yes (2) timing chart data sck stb command 1 command 2 t stby key req
33 m m m m pd16432b package information (unit: mm) 100 pin plastic tqfp (fine pitch) ( 14) item millimeters inches a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 s100gc-50-9eu-1 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.0?.1 0.039 +0.005 ?.004 q 0.1?.05 0.004?.002 +0.055 ?.045 b c d j h i g f p n l k m q r r3 3 +7 ? +7 ? detail of lead end m 75 76 50 26 25 51 100 1 d f 1.0 16.0?.2 0.630?.008 0.039 g 1.0 0.039 h 0.22 0.009?.002 i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) +0.05 ?.04
34 m m m m pd16432b reference documents nec semiconductor device reliability/quality control system (iei-1212) semiconductor device mounting technology manual (c10535e)
35 m m m m pd16432b [memo]
m m m m pd16432b no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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